An important component of any computer system is the memory where data is stored. A commonly used memory module is a so-called dynamic random access memory, or DRAM module. The internal organization of a DRAM module can be viewed as a matrix of memory elements, arranged in rows and columns. Currently, the most frequently used DRAM modules are either of a symmetric type, with an equal number of rows and columns, or of an asymmetric type, in which the ratio of the number of rows to the number of columns is a power of four.
A particular memory element of an ordinary memory module is usually accessed by selecting an address containing a certain number of bits and either reading from or writing to that original address in memory. For a symmetric DRAM module of a given size, however, only half of the original address bits are available for accessing the memory. An address multiplexer is used to access the desired memory element by multiplexing (splitting) the original address into a row address and a column address, each with exactly half the bits of the original address. Conceptually, this can be viewed as mapping a certain set of bits to two smaller subsets of bits. A row address strobe and a column address strobe, synchronized with the output of the address multiplexer, indicate to the DRAM module whether the bits being presented to it at a given time identify the desired row or column. Once both a row and a column have been presented to the DRAM module, a value is either extracted from or written to the chosen memory location, and the operation is complete.
If an asymmetric DRAM module of the same size is employed, then the matrix of memory elements has four, sixteen, or any other power of four, times as many rows as columns. In other words, addressing a particular memory element in the matrix requires two (=log.sub.2 4), four (=log.sub.2 16), or more generally an even number more bits to represent the row than to represent the column. However, the multiplexing circuitry used for symmetric DRAM modules, being configured for an identical number of rows and columns, is not capable of accessing each memory element of an asymmetric DRAM module, and vice versa. Therefore, a circuit card containing DRAM modules has a memory controller and associated wiring which will differ according to the type of DRAM used.
In the telecommunications industry, products, including circuit cards employing DRAM modules, are designed for a long life. Some applications require symmetric DRAM modules, and others require asymmetric DRAM modules. Still other circuit cards use either type of DRAM module depending on variables such as availability, manufacturer and cost. Therefore, different applications could use the same circuit card if only it were not for the two distinct wiring configurations demanded by the two types of DRAM.
It would thus be desirable to simply change between DRAM modules, instead of having to manufacture and support two different types of circuit cards. That is to say, there is a need to design the circuit card so that it can be used, without changing the wiring, with both symmetric and asymmetric DRAM modules.
U.S. Pat. No. 5,600,604 to Chen discloses a scheme whereby a column address decode module is added to the usual memory controller circuitry of a circuit card employing a symmetric single in-line memory module (SIMM). This allows an asymmetric SIMM to replace a symmetric SIMM without requiring a change to the wiring of the circuit card. However, the additional decoder is sensitive to the timing of the circuit, and its complexity increases with the number of memory modules to be accessed. Furthermore, the design is specifically geared towards single in-line memory modules, and not towards DRAM modules in general.